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09005aef80d481d3 pdf/09005aef80d48266 zip asynccellularram_16_32__1.fm - rev. b 9/04 en 1 ?2004 micron technology, inc. all rights reserved. 2 meg x 16, 1 meg x 16 async/page cellularram memory asynchronous cellularram tm mt45w2mw16pafa mt45w1mw16pafa features ? asynchronous and page mode interface random access time: 70ns, 85ns page mode read access sixteen-word page size interpage read access: 70ns, 85ns intrapage read access: 20ns, 25ns v cc , v cc q voltages 1.70v?1.95v v cc 1.70v?3.30v v cc q low power consumption asynchronous read < 20ma intrapage read < 15ma standby: 110a (32mb?standard), 80a (16mb) 90a (32mb?low-power option) deep power-down < 10a low-power features temperature compensated refresh (tcr) on-chip sensor control partial array refresh (par) deep power-down (dpd) mode figure 1: 48-ball vfbga part number example: mt45w2mw16pafa-70lwt options designator configuration 2 meg x 16 mt45w 2 mw16pa 1 meg x 16 mt45w 1 mw16pa vcc core voltage supply: 1.8v vccq i/o voltage: 3.0v, 2.5v, 1.8v package 48-ball vfbga fa 48-ball vfbga?lead-free ba 1 access time 60ns -60 1 70ns -70 85ns -85 standby power standard none low-power (32mb) l options (continued) designator operating temperature range wireless (-30c to +85c) wt 2 industrial (-40c to +85c) it 1 note: 1. contact factory. 2. -30c exceeds the cellularram workgroup 1.0 specification of -25c. a b c d e f g h 1 2 3 4 5 6 top view (ball down) lb# dq8 dq9 v ss q v cc q dq14 dq15 a18 oe# ub# dq10 dq11 dq12 dq13 a19 a8 a0 a3 a5 a17 nc a14 a12 a9 a2 ce# dq1 dq3 dq4 dq5 we# a11 zz# dq0 dq2 v cc v ss dq6 dq7 a20 a1 a4 a6 a7 a16 a15 a13 a10
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32toc.fm - rev. b 9/04 en 2 ?2004 micron technology, inc. all rights reserved. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 part-numbering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 power-up initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 bus operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 page mode read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 lb#/ub# operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 low power operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 standby mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 temperature compensated refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 partial array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 deep power-down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 configuration register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 access using zz# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 software access to the configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 partial array refresh (cr[2:0]) default = full array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 sleep mode (cr[4]) default = par enabled, dpd disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 temperature compensated refresh (cr[6:5]) default = on-chi p temperature sensor . . . . . . . . . . . . . . . . .13 page mode read operation (cr[7]) default = disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 data sheet designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32lof.fm - rev. b 9/04 en 3 ?2004 micron technology, inc. all rights reserved. list of figures figure 1: 48-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: functional block diagram 2 meg x 16 and 1 meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 3: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: power-up initialization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 5: read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 6: write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 7: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 8: software access par functionalit y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 9: load configuration register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 10: software access load configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 11: software access read configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 12: configuration register bit mappi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 13: ac input/output reference wavefo rm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 14: output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 15: power-up initialization period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 16: load configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 17: deep power-down?entry/exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 18: single read operation (we# = v ih ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 19: page mode read operation (we# = v ih ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 20: write cycle (we# control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 21: write cycle (ce# control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 22: write cycle (lb#/ub# control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 23: 48-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32lot.fm - rev. b 9/04 en 4 ?2004 micron technology, inc. all rights reserved. list of tables table 1: vfbga ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 2: bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 3: 32mb address patterns for par (cr[4] = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 4: 16mb address patterns for par (cr[4] = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 5: electrical characteristics and oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 6: temperature compensated refresh specifications and cond itions . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 7: partial array refresh specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 8: deep power-down specifications and conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 9: capacitance specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 10: output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 11: read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 12: write cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 13: load configuration register timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 14: deep power-down timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 15: power-up initialization timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 16: load configuration register timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 17: deep power-down timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 18: read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 19: page mode read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 20: write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 21: write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 22: write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 5 ?2004 micron technology, inc. all rights reserved. general description micron ? cellularram ? products are high-speed, cmos dynamic random access memories that have been developed for low-powe r portable applications. the mt45w2mw16pa is a 32mb device organized as 2 meg x 16 bits, and the mt45w1mw16pa is a 16mb device organized as 1 meg x 16 bits. these devices include the industry-standard, asynchronous memory interface found on other low-power sram or pseudo sram offerings. operating voltages have been reduced in an effort to minimize power consumption. the core voltage has been reduced to a 1.80v operating level. to maintain compatibility with different memory bus interfaces, cellularram devices are avai lable with i/o voltages of 3.0v, 2.5v, or 1.8v. a user-accessible configuration register (cr) defines how the cellularram device performs on-chip refresh and whether page mode read accesses are per- mitted. this register is au tomatically loaded with a default setting during power-up and can be updated at any time during normal operation. to operate seamlessly on an asynchronous memory bus, cellularram products incorporate a transparent self refresh mechanism. the hidden refresh requires no additional support from the system memory con- troller and has no significan t impact on device read/ write performance. special attention has been focused on current con- sumption during self refresh. cellularram products include three system-accessible mechanisms to mini- mize refresh current. temperature compensated refresh (tcr) uses an on-chip sensor to adjust the refresh rate to match the device temperature. the refresh rate decreases at lower temperatures to mini- mize current consumption during standby. tcr can also be set by the system for maximum device temper- atures of +85c, +45c, and +15c. setting sleep enable (zz#) to low enables one of two low-power modes: partial array refresh (par); or deep power-down (dpd). par limits refresh to only that part of the dram array that contains essential data. dpd halts refresh operation altogether and is used when no vital information is stored in the device. these three refresh mechanisms are accessed through the cr. figure 2: functional block di agram 2 meg x 16 and 1 meg x 16 note: functional block diagrams illu strate simplified device oper ation. see truth table, ball de scriptions, and timing diagrams for detailed information. a[20:0] (for 32mb) a[19:0] (for 16mb) input/ output mux and buffers control logic 2,048k x 16 (1,024k x 16) dram memory array dq[7:0] dq[15:8] address decode logic lb# ub# ce# we# oe# zz# configuration register (cr)
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 6 ?2004 micron technology, inc. all rights reserved. note: 1. when lb# and ub# are in select mode (l ow), dq[15:0] are affected. when lb# only is in select mode, only dq[7:0] are affected. when ub# only is in the se lect mode, dq[15:8] are affected. 2. when the device is in standby mode, control inputs (we#, oe#), address inputs, and data inputs/outputs are internally isolated from any ex ternal influence. 3. when we# is invoked, the oe# in put is internally di sabled and has no effect on the i/os. 4. the device will cons ume active power in this mode whenever addresses are changed. 5. v in = v cc q or 0v; all device balls must be static (unswitche d) in order to achieve minimum standby current. 6. dpd is enabled when configur ation register bit cr[4] is ?0?; otherwise, par is enabled. table 1: vfbga ball descriptions vfbga ball assignment symbol type description a3, a4, a5, b3, b4, c3, c4, d4, h2, h3, h4, h5, g3, g4, f3, f4, e4, d3, h1, g2, h6 a[20:0] input address inputs: inputs for the address acce ssed during read or write operations. the address lines are also used to define the value to be load ed into the cr. on the 16mb device, a20 (ball h6) is not internally connected. a6 zz# input sleep enable: when zz# is low, the cr ca n be loaded or the device can enter one of two low-power modes (dpd or par). b5 ce# input chip enable: activates the device when low. when ce# is high, the device is disabled and goes into standby power mode. a2 oe# input output enable: enables the output buffers when low. when oe# is high, the output buffers are disabled. g5 we# input write enable: enables write operations when low. a1 lb# input lower byte enable. dq[7:0] b2 ub# input upper byte enable. dq[15:8] b6, c5, c6, d5, e5, f5, f6, g6, b1, c1, c2, d2, e2, f2, f1, g1 dq[15:0] input/ output data inputs/outputs. e3 nc ? not internally connected. d6 v cc supply device power supply: (1.70v?1.95v) powe r supply for device core operation. e1 v cc q supply i/o power supply: (1.70v?3.30v) powe r supply for inpu t/output buffers. e6 v ss supply v ss must be connected to ground. d1 v ss q supply v ss q must be connected to ground. table 2: bus operations mode power ce# we# oe# lb#/ub# zz# dq[15:0] 1 notes standby standby h x x x h high-z 2, 5 read active l h l l h data-out 1, 4 write active l l x l h data-in 1, 3, 4 no operation idle l x x x h x 4, 5 par partial array refresh h x x x l high-z 6 dpd deep power-down h x x x l high-z 6 load configuration register active l l x x l high-z
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 7 ?2004 micron technology, inc. all rights reserved. part-numbering information micron cellularram devices are available in several different configurations and densities (see figure 3). figure 3: part number chart note: 1. -30c exceeds the cellularram work group 1.0 specification of -25c. valid part number combinations after building the part number from the part num- bering chart, please go to the micron part marking decoder web site at http://www.micron.com/part- search to verify that the part number is offered and valid. if the device required is not on this list, please contact the factory. device marking due to the size of the package, the micron standard part number is not printed on the top of the device. instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. the abbreviated device marks are cross-referenced to the micron part numbers at http://www.micron.com/partsearch . to view the location of the abbreviated mark on the device, please refer to customer service note, csn-11, ?product mark/label,? at http://www.micron.com/ csn . mt 45 w 4m w 16 pa fa -70 wt es micron technology product family 45 = psram/cellularram memory operating core voltage w = 1.70v?1.95v address locations m = megabits operating voltage w = 1.70v?3.30v bus configuration 16 = x16 read/write operation mode pa = asynchronous/page package codes fa = vfbga (6 x 8 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 48-ball ba = lead-free vfbga (6 x 8 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 48-ball (contact factory) production status blank = production es = engineering sample ms = mechanical sample operating temperature wt = -30?c to +85?c (see note 1) it = -40? to +85?c (contact factory) standby power options blank = standard l = low power access/cycle time 60 = 60ns (contact factory) 70 = 70ns 85 = 85ns
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 8 ?2004 micron technology, inc. all rights reserved. functional description in general, the mt45w2mw16pa device and the mt45w1mw16pa device are high-density alternatives to sram and pseudo sram products, popular in low- power, portable applications. the mt45w2mw16pa contains 33,554,432 bits organized as 2,097,152 addresses by 16 bits. the mt45w1mw16pa contains 16,777,216 bits organized as 1,048,576 addresses by 16 bits. these devices include the industry-standard, asyn- chronous memory interface found on other low-power sram or pseudo sram offerings. page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. power-up initialization cellularram products incl ude an on-chip voltage sensor that is used to laun ch the power-up initializa- tion process. initialization will load the cr with its default setting. v cc and v cc q must be applied simul- taneously, and when they reach a stable level above 1.70v, the device will require 150s to complete its self-initialization process (see figure 4). during the initialization period, ce# should remain high. when initialization is complete, the device is ready for nor- mal operation. figure 4: power-up initialization timing bus operating modes the mt45w2mw16pa and the mt45w1mw16pa cellularram products incorporate the industry-stan- dard, asynchronous interface found on other low- power sram or pseudo sram offerings. this bus interface supports asynchronous read and write operations as well as the bandwidth-enhancing page mode read operation. the specific interface that is supported is defined by the value loaded into the cr. asynchronous mode cellularram products power up in the asynchro- nous operating mode. this mode uses the industry- standard sram control interface (ce#, oe#, we#, lb#/ ub#). read operations (figure 5) are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high. valid data will be driven out of the i/os after the specified access time has elapsed. write operations (figure 6) occu r when ce#, we#, and lb#/ ub# are driven low. during write operations, the level of oe# is a ?don't care?; we# will override oe#. the data to be written will be latched on the rising edge of ce#, we#, or lb#/ub# (whichever occurs first). we# low time must be limited to t cem. figure 5: read operation figure 6: write operation vcc vccq device initialization vcc = 1.7v device ready for normal operation t pu > 150s address valid data ce# don?t care data valid oe# we# lb#/ub# t rc = read cycle time address address valid data ce# don?t care data valid oe# we# lb#/ub# t wc = write cycle time < t cem address
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 9 ?2004 micron technology, inc. all rights reserved. page mode read operation page mode is a performance-enhancing extension to the legacy asynchronous read operation. in page- mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be quickly read by simply changing the low-order address. addresses a[3:0] are used to determine the members of the 16-address cellularram page. any change in addresses a[4] or higher will initiate a new t aa access. figure 7 shows the timing diagram for a page mode access. page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. write op erations do not include comparable page mode functionality. the ce# low time is limited by refresh consider- ations. ce# must not stay low longer than t cem. figure 7: page read operation lb#/ub# operation the lower byte (lb#) enab le and upper byte (ub#) enable signals allow for byte-wide data transfers. dur- ing read operations, enabled bytes are driven onto the dqs. the dqs associated with a disabled byte are put into a high-z state during a read operation. dur- ing write operations, any disabled bytes will not be transferred to the memory array and the internal value will remain unchanged. during a write cycle, the data to be written is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. when both the lb# and ub# are disabled (high) during an operation, the device will disable the data bus from receiving or transmitting data. although the device will seem to be deselected, the device remains in an active mode as long as ce# remains low. data ce# don?t care oe# we# lb#/ub# address address[0] d[1] d[2] d[3] t aa t apa t apa t apa d[0] < t cem address [1] address [2] address [3]
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 10 ?2004 micron technology, inc. all rights reserved. low power operation standby mode operation during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation on the full array. standby operation occurs when ce# and zz# are high. the device will enter a reduced power state during read and write operations where the address and control inputs remain static for an extended period of time. this mode will continue until a change occurs to the address or control inputs. temperature compensated refresh temperature compensated refresh (tcr) allows for adequate refresh at different temperatures. this cellularram device includes an on-chip temperature sensor. when the sensor is enabled, it continually adjusts the refresh rate according to the operating temperature. the on-chip sensor is enabled by default. three fixed refresh rates are also available, corre- sponding to temperature th resholds of +15c, +45c, and +85c. the setting select ed must be for a tempera- ture higher than the case temperature of the cellular- ram device. if the case temperature is +35c, the system can minimize self refresh current consumption by selecting the +45c setting. the +15c setting would result in inadequate refreshing and cause data corrup- tion. partial array refresh partial array refresh (par) restricts refresh opera- tion to a portion of the total memory array. this fea- ture enables the system to reduce refresh current by only refreshing that part of the memory array that is absolutely necessary. the refresh options are full array, one-half array, on e-quarter array, one-eighth array, or none of the array. data stored in addresses not receiving refresh will become corrupted. the map- ping of these partitions can start at either the begin- ning or the end of the address map (tables 3 and 4 on page 14). read and write operations are ignored during par operation. the device only enters pa r mode if the sleep bit in the cr has been set high (cr[4] = 1). par can be initi- ated by bring the zz# ball to the low state for longer than 10s. returning zz# to high will cause an exit from par and the entire array will be immediately available for read and write operations. alternatively, par can be initiated using the cr soft- ware access sequence (see software access to the con- figuration register on page 11). par is enabled immediately upon setting cr[4] to ?1? using this method. however, using software access to write to the cr alters the function of zz# so that zz# low no longer initiates par, although zz# continues to enable writes to the cr. this functional change persists until the next time the device is powered up. (see figure 8.) deep power-do wn operation deep power-down (dpd) operation disables all refresh-related activity. this mode is used when the system does not require the storage provided by the cellularram device. any stored data will become cor- rupted when dpd is entered. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initialization procedure before normal operations can resume. read and write operations are ignored during dpd operation. the device can only enter dpd if the sleep bit in the cr has been set low (cr[4] = 0). dpd is initiated by bringing zz# to the low state for longer than 10s. returning zz# to high will cause the device to exit dpd and begin a 150s initialization process. during this 150s period, the current consumption will be higher than the specified standby levels but consider- ably lower than the active current specification. driving zz# low will place the device in the par mode if the sleep bit in the cr has been set high (cr[4] = 1). the device should not be put into dpd using cr software access. figure 8: software access par functionality no yes power-up to enable par, bring zz# low for 10s. change to zz# functionality. par permanently enabled, independent of zz# level. software load executed?
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 11 ?2004 micron technology, inc. all rights reserved. configuration register operation the configuration register (cr) defines how the cel- lularram device performs its transparent self refresh. altering the refresh para meters can dramatically reduce current consumption during standby mode. page mode control is also embedded into the cr. this register can be updated anytime while the device is operating in a standby state. figure 12 on page 14 describes the control bits used in the cr. at power up, the cr is set to 0010h. access using zz# the cr can be loaded using a write operation immediately after zz# makes a high-to-low transi- tion (figure 9). the values placed on addresses a[20:0] are latched into the cr on the rising edge of ce# or we#, whichever occurs fi rst. lb#/ub# are ?don?t care.? access using zz# is write only. figure 9: load co nfiguration register operation software access to the configuration register the contents of the cr can either be read or modi- fied using a software sequence. the nature of this access mechanism may eliminate the need for the zz# ball. if the software mechanism is used, zz# can simply be tied to v cc q. the port line typically used for zz# control purposes will no longer be required. however, zz# should not be tied to v cc q if the system will use dpd; dpd cannot be enabled or disabled using the software access sequence. the cr is loaded using a four-step sequence con- sisting of two read operations followed by two write operations (see figure 10). the read sequence is virtu- ally identical except that an asynchronous read is performed during the fourth operation (see figure 11). note that a third read cycle of the highest address will cancel the access sequence until a different address is read. the address used during all read and write oper- ations is the highest address of the cellularram device being accessed (1fffffh for 32mb and fffffh for 16mb); the content of this address is changed by using this sequence (note that this is a deviation from the cellularram specification). the data bus is used to transfer data into or out of bits 15?0 of the cr. writing to the cr using the software sequence mod- ifies the function of the zz# ball. once the software sequence loads the cr, the level of the zz# ball no longer enables par operation. par operation will be updated whenever the software sequence loads a new value into the cr. this zz# functionality will continue until the next time the device is powered-up. the operation of the zz# ball is not affected if the software sequence is only used to read the contents of the cr. the use of the software sequence does not affect the ability to perform the standard (zz# controlled) method of loading the cr. address valid ce# zz# we# t < 500ns address
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 12 ?2004 micron technology, inc. all rights reserved. figure 10: software access lo ad configuration register note: 1. the write on the third cycle must be ce# controlled. figure 11: software access r ead configuration register note: 1. the write on the third cycle must be ce# controlled. 2. ce# must be high for 150ns before performing the cycle that reads the configuration register. address (max) address (max) address (max) xxxxh xxxxh cr value in a ddress ce# oe# we# lb#/ub# data don't care read read write 1 write address (max) 0000h address (max) address (max) address (max) xxxxh xxxxh cr value out a ddress ce# oe# we# lb#/ub# data don't care read read write 1 read note 2 address (max) 0000h
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 13 ?2004 micron technology, inc. all rights reserved. partial array refresh (cr[2:0]) default = full array refresh the par bits restrict refresh operation to a portion of the total memory array. this feature allows the sys- tem to reduce current by only refreshing that part of the memory array required by the host system. the refresh options are full array, one-half array, one-quar- ter array, one-eighth array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see tables tabl e 3 and tab le 4 on pag e 14) . sleep mode (cr[4]) default = par enabled, dpd disabled the sleep mode bit determines which low-power mode is to be entered when zz# is driven low. if cr[4] = 1, par operation is enabled. if cr[4] = 0, dpd operation is enabled. par ca n also be enabled directly by writing to the cr using the software access sequence. note that this then disables zz# initiation of par. dpd cannot be enabled or disabled using the software access sequence; this should only be done using zz# to access the cr. dpd operation disables all refresh-related activity. this mode will be used when the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re- enabled, the cellularram device will require 150s to perform an initialization procedure before normal operation can resume. dpd should not be enabled using cr software access. temperature compensated refresh (cr[6:5]) default = on-chip temperature sensor this cellularram device includes an on-chip tem- perature sensor that automa tically adjusts the refresh rate according to the operating temperature. the on- chip tcr is enabled by clearing both of the tcr bits in the refresh configuration register (cr[6:5] = 00b). any other tcr setting enables a fixed refresh rate. when the on-chip temperature sensor is enabled, the device continually adjusts the refresh rate according to the operating temperature. the tcr bits also allow for adequate fixed-rate refresh at three different temperature thresholds (+15c, +45c, and +85c). the setting selected must be for a temperature higher than the case tempera- ture of the cellularram device. if the case tempera- ture is +35c, the system can minimize self refresh current consumption by se lecting the +45c setting. the +15c setting would result in inadequate refreshing and cause data corruption. page mode read operation (cr[7]) default = disabled the page mode operation bit determines whether page mode read operations are enabled. in the power-up default state, page mode is disabled.
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 14 ?2004 micron technology, inc. all rights reserved. figure 12: configuratio n register bit mapping par a4 a3 a2 a1 a0 configuration register address bus 4 1 2 3 0 reserved 6 5 a5 0 1 sleep mode dpd enabled par enabled (default) cr[4] tcr cr[6] cr[5] 11 1 1 00 0 0 maximum case temp. +85?c internal sensor (default) +45?c +15?c a6 20? 8 reserved a[20:8] cr[1] cr[0] par refresh coverage cr[2] sleep must be set to "0" all must be set to "0" a7 7 page 0 1 page mode enable/disable page mode disabled (default) page mode enabled cr[7] full array (default) bottom 1/2 array bottom 1/4 array bottom 1/8 array none of array top 1/2 array top 1/4 array top 1/8 array 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 table 3: 32mb address patterns for par (cr[4] = 1) cr[2] cr[1] cr[0] active section address space size density 0 0 0 full die 000000h?1 fffffh 2 meg x 16 32mb 0 0 1 one-half of die 00000 0h?0fffffh 1 meg x 16 16mb 0 1 0 one-quarter of die 000000h?07ffffh 512k x 16 8mb 0 1 1 one-eighth of die 00 0000h?03ffffh 256k x 16 4mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 10000 0h?1fffffh 1 meg x 16 16mb 1 1 0 one-quarter of die 18 0000h?1fffffh 512k x 16 8mb 1 1 1 one-eighth of die 1c 0000h?1fffffh 256k x 16 4mb table 4: 16mb address patterns for par (cr[4] = 1) cr[2] cr[1] cr[0] active section address space size density 0 0 0 full die 00000h?fffffh 1 meg x 16 16mb 0 0 1 one-half of die 00000h?7ffffh 512k x 16 8mb 0 1 0 one-quarter of die 00000h?3ffffh 256k x 16 4mb 0 1 1 one-eighth of die 00000h?1ffffh 128k x 16 2mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 80000h?fffffh 512k x 16 8mb 1 1 0 one-quarter of die c0000h?fffffh 256k x 16 4mb 1 1 1 one-eighth of di e e0000h?fffffh 128k x 16 2mb
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 15 ?2004 micron technology, inc. all rights reserved. absolute maximum ratings voltage to any ball except v cc , v cc q relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50v to (4.0v or vccq + 0.3v, whichever is less) voltage on v cc supply relative to v ss . . -0.20v to 2.45v voltage on v cc q supply relative to v ss . -0.20v to 4.0v storage temperature . . . . . . . . . . . . . . . . -55 c to 150 c operating temperature (case) wireless (see note 1) . . . . . . . . . . . . . . . -30 c to 85 c industrial . . . . . . . . . . . . . . . . . . . . . . . . . -40 c to 85 c soldering temperature and time 10s (solder ball only) . . . . . . . . . . . . . . . . . . . . . .260 c stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. note: 1. -30c exceeds the cell ularram workgroup 1.0 specification of -25c. note: 1. -30c exceeds the cellularram work group 1.0 specification of -25c. 2. input signals may over shoot to vccq + 1.0v for periods less than 2ns duri ng transitions. 3. v ih (min) value is not aligned with cellularram workgroup 1.0 specification of v cc q - 0.4v. 4. input signals ma y undershoot to vss - 1.0v for peri ods less than 2ns during transitions 5. this parameter is specified with the ou tputs disabled to avoid ex ternal loading effects. th e user must add the current required to drive output capacitanc e expected in the actual system. 6. i sb (max) values measured with par set to full array and tcr set to +85c. in order to achieve low standby current, all inputs must be driven to v cc q or v ss . i sb might be slightly higher for up to 50 0ms after power-up, or after changes to the par array partition. table 5: electrical characteri stics and operating conditions wireless temperature 1 (-30oc t c +85 oc), industrial temperature (-40oc < t c < +85oc) description conditions symbol min max units notes supply voltage v cc 1.70 1.95 v i/o supply voltage v cc q 1.70 3.30 v input high voltage v ih 1.4 v cc q + 0.2 v 2, 3 input low voltage v il -0.2 +0.4 v 4 output high voltage i oh = -0.2ma v oh 0.80 v cc qv output low voltage i ol = 0.2ma v ol 0.20 v cc qv input leakage current v in = 0 to v cc qi li 1 a output leakage current oe# = v ih or chip disabled i lo 1 a operating current asynchronous random read/write v in = v cc q or 0v chip enabled, i out = 0 i cc 1 -70 20 ma 5 -85 17 asynchronous page read i cc 1p -70 15 ma 5 -85 12 standby current v in = v cc q or 0v ce# = v cc q i sb 32mb?std 110 a6 32mb?l 90 16mb 80
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 16 ?2004 micron technology, inc. all rights reserved. note: i tcr (max) values measured with full array refresh. ma x values apply across the full temperature range. note: i par (max) values measured with tcr set to 85c. i par might be slightly higher for up to 500ms after changes to the par array partition. table 6: temperature compensated re fresh specifications and conditions description conditions symbol power tcr setting (cr[6:5]) max units temperature compensated refresh standby current v in = v cc q or 0v, ce# = v cc q i tcr 32mb standard (no desig.) +85c 110 a +45c 80 a +15c 70 a 32mb low-power option (l) +85c 90 a +45c 60 a +15c 55 a 16mb +85c 80 a +45c 50 a +15c 40 a table 7: partial array refresh specifications and conditions description conditions symbol power array partition max units partial array refresh current v in = v cc q or 0v zz# = 0v cr[4] = 1 i par 32mb standard (no desig.) full 110 a 1/2 105 a 1/4 95 a 1/8 95 a 070a 32mb low-power option (l) full 90 a 1/2 85 a 1/4 75 a 1/8 75 a 065a 16mb full 80 a 1/2 70 a 1/4 70 a 1/8 70 a 065a table 8: deep power-down sp ecifications and conditions description conditions symbol typ units deep power-down v in = v cc q or 0v; +25c zz# = 0v cr[4] = 0 i zz 10 a
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 17 ?2004 micron technology, inc. all rights reserved. note: 1. these parameters are verified in device characterization and are not 100% tested. figure 13: ac input/outp ut reference waveform note: 1. ac test inputs are driven at v cc q for a logic 1 and v ss for a logic 0. input rise and fall times (10% to 90%) < 1.6ns. 2. input timing begins at v cc /2. due to the possibility of a difference between v cc and v cc q, the input test point may not be shown to scale. 3. output timing ends at v cc q/2. figure 14: output load circuit table 9: capacitance specifications and conditions description conditions symbol min max units notes input capacitance t c = +25oc; f = 1 mhz; v in = 0v c in 2.0 6.5 pf 1 input/output capacitance (dq) c io 3.0 6.5 pf 1 output test points input 1 v cc q v ss v cc q/2 3 v cc /2 2 dut vccq r1 r2 30pf test point table 10: output load circuit v cc q r1/r2 1.8v 2.7k ? 2.5v 3.7k ? 3.0v 4.5k ?
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 18 ?2004 micron technology, inc. all rights reserved. table 11: read cycle timing requirements parameter symbol -70 -85 units notes min max min max address access time t aa 70 85 ns page access time t apa 20 25 ns lb#/ub# access time t ba 70 85 ns lb#/ub# disable to high-z output t bhz 88ns2 lb#/ub# enable to low-z output t blz 10 10 ns 1 maximum ce# pulse width t cem 88s3 chip select access time t co 70 85 ns chip disable to high-z output t hz 88ns2 chip enable to low-z output t lz 10 10 ns 1 output enable to valid output t oe 20 20 ns output hold from address change t oh 55ns output disable to high-z output t ohz 88ns2 output enable to low-z output t olz 55ns1 page cycle time t pc 20 25 ns read cycle time t rc 70 85 ns
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 19 ?2004 micron technology, inc. all rights reserved. note: 1. high-z to low-z timings are tested wi th the circuit shown in figure 14 on pa ge 17. the low-z timi ngs measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . 2. low-z to high-z timings are tested wi th the circuit shown in fi gure 14 on page 17. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. 3. page mode en abled only. 4. we# low time must be limited to t cem (8s). table 12: write cycle timing requirements parameter symbol -70 -85 units notes min max min max address setup time t as 00ns address valid to end of write t aw 70 85 ns byte select to end of write t bw 70 85 ns ce# high time during write t cph 55ns chip enable to end of write t cw 70 85 ns data hold from write time t dh 00ns data write setup time t dw 23 25 ns chip enable to low-z output t lz 10 10 ns 1 end write to low-z output t ow 55ns1 write cycle time t wc 70 85 ns write to high-z output t whz 88ns2 write pulse width t wp 46 50 ns 4 write pulse width high t wph 10 10 ns write recovery time t wr 00ns
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 20 ?2004 micron technology, inc. all rights reserved. table 13: load configuration re gister timing requirements description symbol -70 -85 units notes min max min max address setup time t as 00ns address valid to end of write t aw 70 85 ns chip deselect to zz# low t cdzz 55ns chip enable to end of write t cw 70 85 ns write cycle time t wc 70 85 ns write pulse width t wp 40 40 ns write recovery time t wr 00ns zz# low to we# low t zzwe 10 500 10 500 ns table 14: deep power-down timing requirements description symbol -70 -85 units notes min max min max chip deselect to zz# low t cdzz 55ns deep power-down recovery t r 150 150 s minimum zz# pulse width t zzmin 10 10 s
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 21 ?2004 micron technology, inc. all rights reserved. timing diagrams figure 15: power-up initialization period figure 16: load con figuration register device ready fo r normal operation vcc, vccq = 1.7v t pu vcc (min) table 15: power-up initializ ation timing requirements parameter symbol -70 -85 units notes min max min max power-up initialization period t pu 150 150 s address zz# t wc t aw t wr t as ce# lb#/ub# t zzwe don?t care we# t wp t cdzz opcode t cw oe# table 16: load configuration re gister timing requirements symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t wc 70 85 ns t aw 70 85 ns t wp 40 40 ns t cdzz 55ns t wr 00ns t cw 70 85 ns t zzwe 1050010500ns
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 22 ?2004 micron technology, inc. all rights reserved. figure 17: deep power-down?entry/exit zz# ce# t zz (min) don?t care t cdzz t r device ready for normal operation table 17: deep power-down timing parameters symbol -70 -85 units min max min max t cdzz 55ns t r 150 150 s t zz (min) 10 10 s
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 23 ?2004 micron technology, inc. all rights reserved. figure 18: single re ad operation (we# = v ih ) address oe# t rc t aa data-out ce# lb#/ub# t olz t lz don?t care undefined high-z high-z data valid t ohz t ba t bhz t hz t blz t co t oe address valid table 18: read timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t ba 70 85 ns t oe 20 20 ns t bhz 88ns t ohz 88ns t blz 10 10 ns t olz 55ns t co 70 85 ns t rc 70 85 ns t hz 88ns
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 24 ?2004 micron technology, inc. all rights reserved. figure 19: page mode read operation (we# = v ih ) address a[20:4] oe# t aa data-out ce# lb#/ub# t olz t lz don?t care undefined high-z high-z data valid data valid data valid data valid t ohz t ba t bhz t hz t cem t blz t co address a[3:0] t rc t oh t pc address valid t apa t oe table 19: page mode read timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t apa 20 25 ns t oe 20 20 ns t ba 70 85 ns t oh 55ns t bhz 88ns t ohz 88ns t blz 10 10 ns t olz 55ns t cem 88s t pc 20 25 ns t co 70 85 ns t rc 70 85 ns t hz 88ns
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 25 ?2004 micron technology, inc. all rights reserved. figure 20: write cycle (we# control) address we# t wc t aw t wr data-in ce# lb#/ub# t bw t whz t ow t dh t dw t as t wp t wph don?t care high-z data-out data valid t cw oe# address valid table 20: write timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t ow 55ns t aw 70 85 ns t wc 70 85 ns t bw 70 85 ns t whz 88ns t cw 70 85 ns t wp 46 50 ns t dh 00ns t wph 10 10 ns t dw 23 25 ns t wr 00ns
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 26 ?2004 micron technology, inc. all rights reserved. figure 21: write cycle (ce# control) address we# t wc t aw t cw t wr t cph data-in ce# lb#/ub# t bw t whz t lz t as t dh t dw t wp don?t care high-z data-out data valid address valid oe# table 21: write timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t dw 23 25 ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t cph 55ns t whz 88ns t cw 70 85 ns t wp 46 50 ns t dh 00ns t wr 00ns
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 27 ?2004 micron technology, inc. all rights reserved. figure 22: write cycle (lb#/ub# control) address we# t wc t aw t wr data-in ce# lb#/ub# t bw t whz t dh t as t dw t lz don?t care data-out data valid address valid t cw oe# high-z table 22: write timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t dw 23 25 ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t cw 70 85 ns t whz 88ns t dh 00ns t wr 00ns
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 28 ?2004 micron technology, inc. all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks of micron technology, inc. cellularram is a trademark of micron technology, inc. inside the u.s. and a trademark of infineon technologies outside the u.s. all other trademarks are the property of their respective owners. figure 23: 48-ball vfbga note: 1. all dimensions in millimeters, max/min or typical where noted. 2. package width and length do not in clude mold protrusion; allowable mold protrusion is 0.25mm per side. data sheet designation release (no marking): this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. ball a1 id 1.00 max 4.00 0.05 3.00 0.05 1.875 6.00 0.10 c l c l solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3% ag, 0.5% cu solder ball pad: ?0.30 solder mask defined mold compound: epoxy novolac substrate material: plastic laminate 0.75 typ 0.75 typ 8.00 0.10 5.25 2.625 0.05 ball a1 ball a1 id 3.75 0.70 0.05 seating plane 0.10 c c ball a6 solder ball diameter refers to post reflow condition. the pre-reflow diameter is ?0.35. 48x ?0.37
2 meg x 16, 1 meg x 16 async/page cellularram memory 09005aef80d481d3 pdf/09005aef80d48266 zip micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram_16_32__2.fm - rev. b 9/04 en 29 ?2004 micron technology, inc. all rights reserved. revision history rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/04 clarified ce# low time limited by refresh?must not stay low longer than t cem. changed par options to full, one-half, one-quarter, one-eighth, or none. clarified address a[4] and higher in page mode. clarified i cc and updated values and symbols. updated i cc values. changed c in and c io max values to 6.5pf. changed c in and c io min values. changed t cem max to 8. deleted appendix a (extended timings and all references). changed doc status to ?production.? replaced abbreviated component marks with part numbering chart. corrected package nomenclature to vfbga. added measurement time clarification to i sb and i par notes. updated i sb , i tcr , and i par to production values. renamed t ceh to t cph. noted software access third cycle must be ce#- controlled write. last address changed by software sequence. we# low limited to t cem. clarified tcr temperatures and setting in table 6. changed v cc q option w to 1.7?3.3v. changed wireless temperature to -30c. clarified software access. noted input high voltage not aligned with the workgroup specification of v cc q - 0.4. noted wireless temp (min) exceeds the workgroup spec. rev. a, advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/04 corrected typographic error in software access description. last address not changed by software access sequence. added on-chip sensor to tcr. clarified software access description.

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